1. Field of the Invention
The invention relates to a chip structure, a stacked chip package and a method for manufacturing chip structures and more particularly, to a chip structure with pedestals, a stacked chip package with the above chip structure and a method for manufacturing chip structures with pedestals.
2. Description of the Related Art
In the electronics industry, as products become smaller and smaller, increased miniaturization of integrated circuit (IC) packages has become more and more critical. At the same time, higher performance and lower cost have become essential for new products.
In order to put more integrated circuit chips in a single package to reduce the profile of the product, the manufacturers in the art have begun to stack chips on each other. It is required for these chips to have a gap between them for wire bonding. The gap can be achieved by means of a thick layer of organic adhesive or in combination with inorganic spacers of material such as silicon, ceramic, or metal. However, the above stacked chips with organic or inorganic spacers all are manufactured with more complicated process.
Referring to FIG. 1, in order to solve the above problems, the U.S. Pat. No. 7,242,101 has disclosed a chip 100 with pedestals. The four corners of the back surface 112 of the rectangular chip 100 are respectively positioned with four rectangular pedestals 122, wherein two of the four sides of the each pedestal 122 are respectively coplanar with two of the four side surfaces of the chip 100. When the chip 100 is stacked on other chip, the pedestals 122 are disposed on the active surface of the lower chip to achieve a gap between the two chips for wire bonding. However, the pads for wire bonding are typically positioned on the edge of the active surface of a chip. Thus, the pedestals 122 will be always positioned on the bonding pads of a lower chip when the chip 100 is attempted to be stacked on the substantially equally-sized lower chip. This will cause the lower chip not to be wire bonded.
Accordingly, there exists a need to provide a chip structure to solve the above-mentioned problems.